chifalcon
Newbie level 6
Hi,
I need to generate a couple of clocks which has fixed and adjustable phaseshift. One frequency is 2 times of the other one. e.g. in my case, one frequency is 3Mhz, one is 6Mhz. I use DCM due to it's merit of high phase shift resolution.
Becasue my design work in LFM (low frequency mode), I cannot directly generate the two clocks from CLKIN and CLKDV(or CLKFX). becasue in LFM, if using CLKIN in LF, only CLKFX can be used. however CLKFX cannot be lower than 32Mhz. So I used a FSM to generate the other LF clock by frequency-dividing the output of DCM.
I am planning to do it like this:
Here, if i use the 6Mhz signal as the feedback to CLKFB, can the 6Mhz clocks be aligned with the 3MHz clock? I mean, whether the phaseshift of 3Mhz and 6Mhz signal be fixed ?
Sorry, forgot to say, my target device is Xilinx Virtex5.
Thanks very much!
I need to generate a couple of clocks which has fixed and adjustable phaseshift. One frequency is 2 times of the other one. e.g. in my case, one frequency is 3Mhz, one is 6Mhz. I use DCM due to it's merit of high phase shift resolution.
Becasue my design work in LFM (low frequency mode), I cannot directly generate the two clocks from CLKIN and CLKDV(or CLKFX). becasue in LFM, if using CLKIN in LF, only CLKFX can be used. however CLKFX cannot be lower than 32Mhz. So I used a FSM to generate the other LF clock by frequency-dividing the output of DCM.
I am planning to do it like this:
Here, if i use the 6Mhz signal as the feedback to CLKFB, can the 6Mhz clocks be aligned with the 3MHz clock? I mean, whether the phaseshift of 3Mhz and 6Mhz signal be fixed ?
Sorry, forgot to say, my target device is Xilinx Virtex5.
Thanks very much!