What do you mean, if by port you mean the pins of the chip then you can read them if you declare them as buffer output or inout input/output or if you can use an out output and use a signal that stores the last value that was sent to the output and read it from anywhere.
I'm only using VHDL so i don't know anything about verilog
For example,
entity gcd is
port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned(3 downto 0);
y_i: in unsigned(3 downto 0);
d_o: out unsigned(3 downto 0)
);
end gcd;
her the output port "d_o" cannot be read inside the architecture. some thing like "data <= d_o"; you have to do indirectly.
But this is allowed in Verilog. My colleague says it is wrong to use even it is allowed.
entity gcd is
port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned(3 downto 0);
y_i: in unsigned(3 downto 0);
d_o: buffer unsigned(3 downto 0)
);
end gcd;
you can read it.
I'm sure it can be done in verilog too but i can't say how.
In verilog it is possible to read the output without any modification.
Again my question is "In Verilog reading ouput diretly is wrong , even though it is allowed. - Why?"
He assigns a value to a port defined as output and then in another part of the code he uses a condition for example which reads the value of that port and does something.
He is asking why is it wrong to read (directly) the value of a port defined as output .
I did some research and i found that some people are against declaring a port as buffer and say that you should always declare it as out and use a driver signal which you can read, this is for VHDL
I assume that what your friend told you is the same thing for verilog.