Reading the a VHDL text file in a loop

[shaiko]

Hello,

I have the following text file:

0 1 2 4
5 6 7 8
9 10 11 12

The following code reads the file successfully from start to end:

reading_from_file : process ( IN_GLOBAL_RESET , IN_CLOCK ) is
file text_file : text open read_mode is "C:\some_file.txt" ;
variable current_line : line ;
variable incoming_data : integer ;
variable data_coutner : integer := 0 ;
begin
    if IN_GLOBAL_RESET = '1' then
        data <= ( others => '0' ) ;
	elsif rising_edge ( IN_CLOCK ) then
        if not endfile ( text_file ) then
            if data_coutner = 0 then
                readline ( text_file , current_line ) ;
            end if;
            read ( current_line , incoming_data ) ;  
            data <= std_logic_vector ( to_unsigned ( incoming_data , data ' length ) ) ;	
            data_coutner := ( data_coutner + 1 ) rem 4 ;	
        end if ;
    end if ;		
end process reading_from_file ;

How should I modify the above code so it would roll back to the begging as soon as it reaches the end of file (essentially reading the same file in an infinite loop) ?

 

[TrickyDicky]

If you close the file, then re-open it, it will start again.
Instead of opening the file at the start, use the FILE_OPEN and FILE_CLOSE procedures during the process.