yes i am reading it as integer, and i want the 2nd format you mentioned: MSB to be the sign, and the rest to be the unsigned version of the number. i will post my code later as i am making some changes. So if i read the number -5 for example i want the msb to be 1, and the rest to be 101.it sounds like you are reading these in as binary? how about reading them in as integers? its perfectly possible to read these from a text file:
10
11
-111
-99
--etc
and from this you can convert it to any type you like. But the number format you are talking about - what you describe is almost 2s compliment - is that what you mean. Or do you need a special format where the MSB is the sign and the rest is an unsigned version of the number. if so, why not 2s compliment, as that is the standard used by everything.
What code have you got so far? how are your input files formatted?
to_be_squared<=abs(conv_integer(signed(temp_out_dif)));
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
type error resolving prefix expression abs as type " IEEE.std_logic_1164.STD_LOGIC_VECTOR"
ok now i want to turn my negative number in its abs, and i am using the following:
where temp_out_diff is of type std_logic_vector.. It doesn't work either with the type cast, either without it.. I have included the following packagesCode:to_be_squared<=abs(conv_integer(signed(temp_out_dif)));
Code:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
and this is my error message:
Code:type error resolving prefix expression abs as type " ieee.std_logic_1164.std_logic_vector"
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity tb_file_square_dif is
generic
(
N :integer := 8
);
end tb_file_square_dif;
architecture TB_ARCHITECTURE of tb_file_square_dif is
file IN_VECTORS: TEXT open READ_MODE is "input.txt";
file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";
--here
component squaredif_n
port(
a,b: in signed(N-1 downto 0);
bin: in std_logic;
clk:in std_logic;
d: out signed(2*N-1 downto 0);
bout: out std_logic);
end component;
signal a,b: signed(N-1 downto 0);
signal bin,clk: std_logic;
signal d:signed(2*N-1 downto 0);
signal bout: std_logic;
begin
UUT: squaredif_n
port map (
a=>a,
b=>b,
bin=>bin,
clk=>clk,
d=>d,
bout=>bout);
process
variable IN_BUF: LINE;
variable OUT_BUF: LINE;
variable clk_var,bin_var,bout_var : bit;
variable a_var,b_var : bit_vector(N-1 downto 0);
variable dout_var:bit_vector(2*N-1 downto 0);
begin
while not ENDFILE(IN_VECTORS) loop
READLINE(IN_VECTORS,IN_BUF);
READ(IN_BUF,a_var);
READ(IN_BUF,b_var);
bin<='0';
read_inp: for k in 0 to N-1 loop
a(k)<=to_stdulogic(a_var(k));
b(k)<=to_stdulogic(b_var(k));
end loop;
wait for 1 ms;
WRITE(OUT_BUF,STRING'("SQUARE DIFFERENCE IS= "));
WRITE(OUT_BUF,conv_integer(d));
WRITELINE(OUT_VECTORS,OUT_BUF);
end loop;
wait;
end process;
process
begin
clk<='0';
wait for 10 ns;
clk<='1';
wait for 10 ns;
end process;
end TB_ARCHITECTURE;
1)ok to conclude, if i want to my read function to return only the -234 (if my initial reading value is -0.000234) what conversion do i have to make?
variable a_real: real;
...
read (in_buf,a_real);
a <= conv_unsigned(integer(a_real*1.0**6),N);
it's just a file with binary values.can you provide the input file?
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