signal stream_data : a2_std_logic_vector_type(39 downto 0)(6 downto 0)(9 downto 0);
signal din_anc : std_logic_vector(9 downto 0);
create_SDI_stream : process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
begin
file_open(file_anc,"file_anc.txt", read_mode);
if not endfile(file_anc) then
for i in 0 to 39 loop
readline(file_anc,anc_line);
for j in anc_line'range loop
hread(anc_line,anc_data);
stream_data(to_integer(anc_line))(j) <= anc_data;
wait for 1 ps;
end loop;
end loop;
end if;
file_close(file_anc);
end process;
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
I'm not a VHDL expert so I can't be sure what the error means. But I do notice the if statement isn't doing anything as opening the file then checking for end of file is a rather useless check. The first for loop will run out of data as the file has less lines than the number of times through the loop.# Stopped at /home/yash/workspace/video_anc_generic/sim/tb_generic_anc_extractor.vhd 118 ForLoop loop
how can I solve it?
file file_anc : text;
signal din_anc;
signal video_clk;
constant video_clk_period : time := 7 ns; -- frequncy of 3g sdi / 1 sec
begin
create clock: process
begin
video_clk <='0';
wait for video_clk_period/2;
video_clk <='1';
wait for video_clk_period/2;
end process;
create serial data: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
begin
file_open(file_anc,"file_anc.txt", read_mode);
if not endfile(file_anc) then
for j in anc_line'range loop
hread(anc_line,anc_data);
din_anc<= anc_data;
wait until rising_edge(video_clk);
end loop;
end if;
file_close(file_anc);
end process;
## file_anc.txt
000 FF1 3F0 3F1 001 CD0 CF0 FD0 DC1
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 create serial data: process variable anc_line : line; variable anc_data : std_logic_vector(9 downto 0); variable good : boolean; begin file_open(file_anc,"file_anc.txt", read_mode); while not ENDFILE(file_anc) loop readline(file_anc, anc_line); hread(anc_line,anc_data, good); while good loop din_anc<= anc_data; wait until rising_edge(video_clk); hread(anc_line,anc_data, good); end loop; end loop; file_close(file_anc); wait; end process;
I dont quite understand your problem now though. Are you asking for help with code in #1 or #3?
architecture behav of tb is
signal array : a_std_logic_vector_type (data_counter downto 0)(9 downto 0); -- POINT 1
signal dout : std_logic_vector(9 downto 0);
begin
create_enable: process (video_clk)
begin
if rising_edge(video_clk) then
if vcount = true and hcount = 0 then
read_line_enable <= '1';
else
read_line_enable <= '0';
end if;
-- insert data
if hcount <= data_counter then
dout <= array(data_counter); -- POINT 2
din_anc <= dout;
else
dout <= "00"&x"20";
din_anc <= dout;
-- hcount_d <= hcount;--for data synchornisation
end if;
end if;
end process;
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean;
begin
file_open(file_anc, "file_anc.txt", read_mode);
if read_line_enable = '1' then
readline(file_anc, anc_line);
hread(anc_line, anc_data, data_available);
while (data_available = true) loop
hread(anc_line, anc_data, data_available);
data_counter <= data_counter + 1;
array(data_counter) <= anc_data; -- POINT 3
end loop;
data_counter <= 0;
end if;
file_close(file_anc);
wait;
end process;
near "array": expecting IDENTIFIER :: POINT 1
near "array": syntax error :: POINT 2,3
architecture behaviour of tb_generic_anc_extractor is
file file_anc : text;
----------------------- other code
signal din_anc : std_logic_vector(9 downto 0);
signal hcount : integer := 0;
signal data_counter : integer := 0;
signal vcount : boolean := false;
signal read_line_enable : std_logic := '0';
type anc_array is array (0 to data_counter) of std_logic_vector(9 downto 0);
signal arr : anc_array;
signal dout : std_logic_vector(9 downto 0);
begin
create_enable: process (video_clk)
begin
if rising_edge(video_clk) then
if vcount = true and hcount = 0 then
read_line_enable <= '1';
else
read_line_enable <= '0';
end if;
-- insert data
if hcount <= data_counter then
din_anc <= arr(data_counter);
else
din_anc <= "00"&x"20";
-- hcount_d <= hcount;--for data synchornisation
end if;
end if;
end process;
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean;
variable result : anc_array(others=>(others=>'0'));
begin
file_open(file_anc, "file_anc.txt", read_mode);
if read_line_enable = '1' then
readline(file_anc, anc_line);
hread(anc_line, anc_data, data_available);
while (data_available = true) loop
hread(anc_line, anc_data, data_available);
result(data_counter) := anc_data; -- arr(data_counter) <= anc_data; or using this
data_counter <= data_counter + 1;
wait until rising_edge(video_clk);
end loop;
-- data_counter <= 0;
end if;
file_close(file_anc);
wait;
end process;
create_hcount : process(video_clk)
begin
if falling_edge(video_clk) then
if fw_dvalid = '1' then --when data is valid
hcount <= to_integer(unsigned(fw_hcount))+1; -- create a integer pointer for fw_hcount to compare later
end if; -- +1 for timing synchronisation
end if; -- fw :- framework
end process;
create_vcount : process(video_clk) -- will create a case statement for later addition of vcount select
begin
if rising_edge(video_clk) then -- checking at falling edge
if fw_vcount <= "00000000000" then -- checking if vcount reach 0
vcount <= true; -- assigning boolean value true.
else
vcount <= false;
end if;
end if;
end process;
end architecture;
What do you mean by "doesnt seem to open"? Does it throw an error about the file not existing? Is there no stimulus? Please explain the problem or show the error.
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean;
-- variable result : anc_array(others=>(others=>'0'));
begin
file_open(file_anc, "file_anc.txt", read_mode);
if read_line_enable = '1' then
readline(file_anc, anc_line);
hread(anc_line, anc_data, data_available);
while (data_available = true) loop
hread(anc_line, anc_data, data_available);
-- result(data_counter) := anc_data;
data_counter <= data_counter + 1;
arr(data_counter) <= anc_data;
wait until rising_edge(video_clk);
end loop;
-- data_counter <= 0;
end if;
file_close(file_anc);
wait;
end process;
(vcom-1013) Type "anc_array" depends on value of signal "data_counter"
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean;
variable result : anc_array;
begin
file_open(file_anc, "file_anc.txt", read_mode);
if read_line_enable = '1' then
readline(file_anc, anc_line);
hread(anc_line, anc_data, data_available);
while (data_available = true) loop
hread(anc_line, anc_data, data_available);
result(data_counter) := anc_data;
data_counter <= data_counter + 1;
wait until rising_edge(video_clk);
end loop;
data_counter <= 0;
end if;
file_close(file_anc);
wait;
end process;
(vcom-1013) Type "anc_array" depends on value of signal "data_counter".
You should not create a type from a signal. Your array is only length 1 (0 downto 0). You should use some constant value to set the length of the type
type anc_array is array (0 to 9) of std_logic_vector(9 downto 0);
begin
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean;
variable result : anc_array;
variable count : integer := 0;
begin
file_open(file_anc, "file_anc.txt", read_mode);
if read_line_enable = '1' then
readline(file_anc, anc_line);
hread(anc_line, result(0), data_available);
while (data_available = true) loop
for result'range loop
hread(anc_line, anc_data, data_available);
result(i) := anc_data;
data_counter <= count + 1;
end loop;
wait until rising_edge(video_clk);
end loop;
end if;
file_close(file_anc);
wait;
end process;
You should not create a type from a signal. Your array is only length 1 (0 downto 0). You should use some constant value to set the length of the type
Maybe not a good solution, but it should be possible to initialize the constant from a function that makes a separate "pre-read" of the file to check how much data there is.
type anc_array is array (0 to 2000) of std_logic_vector(9 downto 0);
signal arr : anc_array;
file file_anc : text;
signal data_counter : integer := 0;
data_count: process
variable anc_line : line;
variable anc_data : std_logic_vector(9 downto 0);
variable data_available : boolean := true;
variable count : integer := 0;
begin
file_open(file_anc, "file_anc.txt", read_mode); -- open file
while not endfile(file_anc) loop
wait until read_line_enable = '1'; -- Reading one line condition
if data_available = true then --cheching if there is any more data on your line
count:= 0; -- return false when no more data on line
data_counter <= 0; -- this makes your conter wrap back to 0
end if;
while (data_available = true) and data_counter<arr'length loop -- LOops till the last data in one line is reached
hread(anc_line, anc_data, data_available); -- redaing one data from the line
arr(count) <= anc_data; -- text file data being fed to the array.
count := count+1;
data_counter <= count; -- counting the no. of data values in one line. Will be used later
wait for 1 ns; -- exit when no data is present in the text line
end loop;
end loop;
file_close(file_anc);
wait for 1 ps;
end process;
I'm more inclined to believe you didn't follow what I wrote about above.Hi,
Nope you are getting it all wrong.
I've used VHDL for decades and I've never needed to add a 1ns delay into a file reading process that loaded an array. Yes I've used time control or wait for clock edges or other signals when I didn't use an array and read the data directly into the testbench when it was needed for excessively large sets of data vectors.The code reads all the data in one line. That is
TEXT FILE:-
000 3FF 311 322
3FF 000 111 222
Then the code would put all the values of first line in the array. And reads next line when your condition is true. I have declared size of my array cause thats the max amount of data I want to output serially. Remember this is simulation, so your array size can very large. Then you read the array out by index. Then read again to over write the array. This way we don't have to either care about the size of line or no. of lines. Its fully automated.
I have used 1 ns delay, because without it was not working correctly. So you can always see if you can do away with 1 ns statements in your code if it works good.
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