I notice that this isn't the very first FPGA code you are dealing with, although one could suspect at first sight.
So you can you refer to things you have learned before.
A for loop doesn't constitute a sequence in time, instead it goes through all iteration steps at once, in a single clock cycle. Your code ends up with writing the last target_reg value to the FIFO, skipping all previous ones.
To write all bytes one by one you have to design a state machine.