reading binary files in VHDL

[lijing8898]

HI all,

I am facing problems with reading binary files in VHDL. I want to make a ROM with the size 512*8bit. Firstly, initialing the ROM and then reading data.

Here is the code and error message I have got. I am expecting answers.

***************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;

entity ram_t is
port(
adr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(3 downto 0));
end ram_t;

architecture Behavioral of ram_t is

file file_in: text;
variable f_status: FILE_OPEN_STATUS;
TYPE memory IS ARRAY (0 to 512) OF std_logic_vector(3 downto 0);
signal weight : memory;
signal startup: boolean := true;
variable index : integer:= 0;
variable buf : line;

begin
file_open(f_status, file_in, "STD_IN.txt", read_mode);
process
begin
if startup then
for j in weight' range loop
readline(file_in,buf);
read (buf, weight(j));
end loop;
startup <= false;
end if;
data_out <= weight(conv_integer(adr));
end process;
end Behavioral;

************************************
error message is "Line 30: read expects 3 arguments.
Line 30: Type void is not an array type and cannot be indexed."

ps: "line 30" is " read (buf, weight(j)); "
*********************************
Here is the binary file, "STD_IN.txt"

1111
0000
0011
1100
0001
.....

 

[FvM]

I am expecting answers

- Review the textio library definition of your VHDL tool for supported types and arguments.
- If you want to use the ROM for synthesis, check if your VHDL tool supports textio for initialization. Many tools doesn't.

This is not 512*8bit:

TYPE memory IS ARRAY (0 to 512) OF std_logic_vector(3 downto 0);

 

[TrickyDicky]

1. As you are trying to read directly into a std_logic_vector, you need to use ieee.std_logic_textio aswell as std.textio.
2. You need a wait at the end of the process, else its going to keep opening and closing the file forever.
3. It is also very very innefficent to read the entire file every time you want to read a single address. Read the file once into an array and access it like that.
4. FILE_OPEN has to be inside a process/procedure/function.
5. Variables cannot exist inside architectures, only process/procedure/function.

 

[jducluzeau]

Concerning simulation, you can load file directly under your simulator
I don(t remember the exact syntax but under modelsim it is something like this :
load path/ram file_name

Regards,
Jerome