bachoo786
Junior Member level 1
Hello there,
I have got this code for reading data from a text file into a RAM. I get this warning "net mem [0][7] does not have a driver." Can anyone please have a look at my code, if I am missing something? Many thanks !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity rom is
port (
clk :in std_logic; -- Clock
read_en :in std_logic; -- Read enable
address :in std_logic_vector (7 downto 0); -- Address input
data ut std_logic_vector (7 downto 0) -- Data output
);
end entity;
architecture behavior of rom is
-- RAM block 8x256
type RAM is array (integer range <>) of std_logic_vector (7 downto 0);
signal mem : RAM (0 to 255);
-- Instructions to read a text file into RAM --
procedure Load_ROM (signal data_word :inout RAM) is
-- Open File in Read Mode
file romfile :text open read_mode is "memory.txt";
variable lbuf :line;
variable i :integer := 0;
variable fdata :std_logic_vector (7 downto 0);
begin
while not endfile(romfile) loop
-- read data from input file
readline(romfile, lbuf);
read(lbuf, fdata);
data_word(i) <= fdata;
i := i+1;
end loop;
end procedure;
begin
process(clk,read_en,mem)
begin
-- Procedural Call --
Load_ROM(mem);
if(clk'event and clk = '1') then
if(read_en='1')then
data <= mem(to_integer(unsigned(address)));
else
data <="ZZZZZZZZ";
end if;
end if;
end process;
end architecture;
I have got this code for reading data from a text file into a RAM. I get this warning "net mem [0][7] does not have a driver." Can anyone please have a look at my code, if I am missing something? Many thanks !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity rom is
port (
clk :in std_logic; -- Clock
read_en :in std_logic; -- Read enable
address :in std_logic_vector (7 downto 0); -- Address input
data ut std_logic_vector (7 downto 0) -- Data output
);
end entity;
architecture behavior of rom is
-- RAM block 8x256
type RAM is array (integer range <>) of std_logic_vector (7 downto 0);
signal mem : RAM (0 to 255);
-- Instructions to read a text file into RAM --
procedure Load_ROM (signal data_word :inout RAM) is
-- Open File in Read Mode
file romfile :text open read_mode is "memory.txt";
variable lbuf :line;
variable i :integer := 0;
variable fdata :std_logic_vector (7 downto 0);
begin
while not endfile(romfile) loop
-- read data from input file
readline(romfile, lbuf);
read(lbuf, fdata);
data_word(i) <= fdata;
i := i+1;
end loop;
end procedure;
begin
process(clk,read_en,mem)
begin
-- Procedural Call --
Load_ROM(mem);
if(clk'event and clk = '1') then
if(read_en='1')then
data <= mem(to_integer(unsigned(address)));
else
data <="ZZZZZZZZ";
end if;
end if;
end process;
end architecture;