vGoodtimes,
Code:
type memory_matrix is array 0 to x of std_logic_vector(y downto 0);
signal memory:memory_matrix;
process(clock) is
begin
if rising_edge(clock) then
memory (to_integer(address))<=in_data;
end if;
end process;
out_data<=memory(address);
It successfully infers BRAM in Cyclone IV and Lattice XP devices.
And as I see it, if it passes synthesis and infers a BRAM - this BRAM
must be "read before write".
As this is explicitly described in the VHDL code.
Code:
out_data<=memory(address);--show yourself NOW!
TrickyDicky,
Yes, my design must use a "read before write" memory - why is that an "issue" ?