set search_path " /tools/synopsys_asic/cell_libs "
set link_path " * uk65lscllmvbbh_090c125_wc.db uk65lscllmvbbl_090c125_wc.db "
set power_enable_analysis "true"
set power_analysis_mode "averaged"
# load design
read_ddc design.ddc
link_design -keep_sub_designs top_level
current_design noc_switch_1_1_1
# reading timing constraints
source ./constraints-500.tcl
read_saif file.saif -strip_path testbench/top_level
report_switching_activity -list_not_annotated
check_power
update_power
report_power -hierarchy
I have this results for annotation:
Thanks so much for your answer.
I have a comment please, are you sure the names in the gate-level in Modelsim would be the same names in the gate-level in Design Compiler. Because you know the names are changed from rtl to gate and we do that in both
Modelsim and DC.
Thanks.
So my flow is the following:
1/ Making RTL simulation of my design by Modelsim and generating RTL SAIF file .
2/ synthesis the design using DC and getting netlist A
3/ reading the netlist A and RTL SAIF file by Prime Time to estimate the power.
there is for sure problem in nets annotation because of annotation the names from RTL SAIF file to names after synthesis which are changed. There is "set_rtl_to_gate_name" command in PT but it's very difficult to use it because we should annotate each net separately which take so long time.
So I decided to generate gate-level SAIF file by modelsim by using netlist A which is generated by DC. But I don't know exactly how to do that correctly.
So if you are familiar with gate-level simulation, it would be very kind from you to give me just some useful hints or steps to do that correctly.
Thanks in advance.
Thanks ThisIsNotSam and slutarius for help. Dear slutarius, I didn't mention I need line be line instructions, just I wanted to make sure from the general steps.
Any way I started with your flow that you mentioned above. But actually I just need the following:
1/ Synthesis by DC and it outputs a netlist A and Spef.
2/ running gata-level simulation in Modelsim using netlist A and Spef to get the SAIF file.
3/ calculate power using SAIF file with netlist A
So I mean what I need is to run directly netlist A in Modelsim to generate SAIF file. So I need in Modelsim just:
- My testbench
- Netlist A
- libraries that I used in DC
My question here is: Should I include any thing else in Modelsim to run the gate-level simulation?
Thanks
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