maxporter
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A more or less generic question regarding a RC oscillator. I have inherited a RC oscillator from a colleague, who unfortunately isn’t employed anymore. It’s a switched current mirror (couple of uA), a capacitor (0.5pF) and a comparator with feedback. The comparator output controls the current mirror. Typical the design works perfect, intended frequency is spot-on (app. 20MHz). However when I simulate the design with a parasitic extracted view for the comparator only (so current mirror and capacitor are ideal), then the frequency drops rather much (15-20%). What could be the root cause? Additional parasitic capacitance on the differential pair input? Note: differential pair transistors have minimal length and relative large w.