In verilog we can get the random number by system task $random(seed).
If I don't give a seed, does verilog simulator use system time as the seed
or still simulation time as the seed?
If verilog simulator doesn't use system time as the seed, how do I use
system time as the seed or how do I guarantee to have a real random
numbers?
I mean that I write the testbench which needs to do some random task,
not hardware.
LFSR + XOR is a pseudo-random number generator. It still has order.
You can do it with PLI functions. If you search the forum you can find the PLI documents and explanations about writing C code for generating random numbers.
If you are desining an FPGA and using @ltera, you can use the its internal PLL's noise to generate random number inside FPGA.
In verilog, there is no such true random number, it is a pseudorandom number where the sequence is fixed. If you want to get different random number then you need to change the seed each time you perform simulation.