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# random pulse generator verilog

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#### jiang

verilog random

Hi guys,

In verilog we can get the random number by system task $random(seed). If I don't give a seed, does verilog simulator use system time as the seed or still simulation time as the seed? If verilog simulator doesn't use system time as the seed, how do I use system time as the seed or how do I guarantee to have a real random numbers? Best Regards, Jiang #### andy2000a ##### Advanced Member level 2 verilog$random

please see I2C APR protocol or Plug_&_Play speci
have LFSR + XOR for random number ..

#### jiang

\$random verilog

andy2000a said:
please see I2C APR protocol or Plug_&_Play speci
have LFSR + XOR for random number ..

I mean that I write the testbench which needs to do some random task,
not hardware.
LFSR + XOR is a pseudo-random number generator. It still has order.

#### j2cheng

##### Junior Member level 1
random verilog

I think any random number generated by software will use timer to be its seed. Only hardware can pick up noise as its seed.

j2cheng

#### Laplace

verilog random number

You can do it with PLI functions. If you search the forum you can find the PLI documents and explanations about writing C code for generating random numbers.

If you are desining an FPGA and using @ltera, you can use the its internal PLL's noise to generate random number inside FPGA.

#### skynet

##### Member level 5
random in verilog

Hi jiang,

In verilog, there is no such true random number, it is a pseudorandom number where the sequence is fixed. If you want to get different random number then you need to change the seed each time you perform simulation.

rgds,
SkyNet

#### walkon

##### Junior Member level 1
verilog random seed

How about generate random number with LSFR?

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