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Random Numbers Generator

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StevieChalmers

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I need a random number generator
written in VHDL to generate natural numbers
from 0 to 15. Does anyone have anything
similar to it (like any natural numbers
generator) ?

Any help would be much appreciated.
Thanks in advance.
 

leongch

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hi, if the functions are not synthesizable mean we cant download it onto the fpga and realize it? I want to confirm because my frenz's final year project may require random number generator as part of his project and the project must at the end able to be download into the FPGA and reliaze it... thanks
 

Iouri

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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY psp IS
PORT( clk : in std_logic;
reset : in std_logic;
init_value : in std_logic_vector(8 downto 0);
dout : out std_logic);
END psp;

ARCHITECTURE rus OF psp IS

SIGNAL reg: std_logic_vector(8 downto 0);

BEGIN

process(clk, reset, init_value)
begin
if reset = '1' then
reg <= init_value;
elsif rising_edge(clk) then
reg <= (reg(4) xor reg(0)) & reg(8 downto 1);
end if;
end process;

dout <= reg(0);

END rus;
 

moorthi

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Hi use a 4-Stage de-bruijn sequence generator and take all the four bits as output.
To about de-bruijn genenerator type "de bruijn sequence" in google search.
 

ahmad_abdulghany

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you can simply use any number of D-FF (depending on the word length you need to generate in your random number as number of Flip flops equal to number of bits per word) cascade these FFs with output of last stage connected to the input of first stage after XNOR or XOR gates.. this will generate random numbers of n-bits.. you can then simply use VHDL to get the required code of it..

I hope that helpls..
Ahmad,
 

janovetz

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The HDL code posted above will work, but I would recommend using a longer shift register. Longer registers repeat less frequenty.
 

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