Assuming your full scale voltage is 3V. Your DAC code needs to ramp from 0 to 16383 in 100mS. That means each step occurs in 6.103 microseconds. This does not have a nice integer relation to 5MHz. There are several approaches you can take, such as:
1) Use a PLL (if your FPGA has one)to generate an appropriate sampling frequency. This might not be acceptable due the jitter associated with the PLL.
2) Change your ramp requirement. If you increment your DAC every 31 5MHz clocks, you'll get a ramp time of 101.6mS.
3) Adjust your resolution. If you can accept 13 bits resolution(8192), then you can increment your DAC code by 2 every 61 5MHz clocks. This would give a ramp of 61/5MHz*8192= .9994mS.