dug through old IEEE "red rag" issues from that period
Thank you, going through older books did help a bit.
First, from rough schematics i found, i was able to put together a memory cell as a sequential circuit:
While sufficient, it's too big for comfort if done naive - that's about 8cm^2 per 1 bit.
As far as i understand, only the 4 NANDs are to be replicated in a grid.
2 of these are a latch, which is less than full 2 NANDs of DTL, but other two are full NANDs, and not simplifyable.
Another thing i found (called "bipolar SRAM cell") is this:
A latch with some control stuff around it using "multi-emitter transistors". Does not make much sense to me, looks like something for an IC.
Is that one equivalent to three transistors with bases and collectors linked?
Then, where do inputs go from?
All in all, i'll keep thinking and digging, and ideas are still welcome.
Nobody was using DTL anymore when I got into this business. Why you
want to, I can't imagine. You can get CMOS or TTL latches and registers
and flip-flops for dirt cheap. In tinier packages than DTL will be, surely.
Sure. Then, why use the gate chips if you can buy ALU and control chips for dirt cheap, why use these if you can buy microcontrollers and memory chips as well, or why use parts when you can buy microprocessors and all the peripherals, finally, why not just buy a computer!
I wanted to get an idea how things work on the low level.
RTL don't stack well, DTL have an extra diode, TTL saves you the diode but needs bulkier transistors, and CMOS is weird.