RAM/ROM using VHDL, Am not really getting what to and need help

[axi3795]

Hi Everyone,
I wanna describe a RAM and ROM in VHDL and am not really getting what to do, so I will really appreciate if someone can help me.
Memory
8-Bit Addressable Memory, i.e. 8-bit wide Address Bus;
4-Bit Data-In-Bus;
4-Bit Data-Out-Bus;
One Program Memory Address Space implemented using an initialized ROM.
One Data Memory Address Space implemented using an uninitialized,
asynchronous RAM.
Asynchronous Write signal, MW = 1 to write, 0 to not write, i.e. re

Thank You,

 

[ads-ee]

Hi Everyone,
I wanna describe a RAM and ROM in VHDL and am not really getting what to do, so I will really appreciate if someone can help me.
Memory
8-Bit Addressable Memory, i.e. 8-bit wide Address Bus;
4-Bit Data-In-Bus;
4-Bit Data-Out-Bus;
One Program Memory Address Space implemented using an initialized ROM.
One Data Memory Address Space implemented using an uninitialized,
asynchronous RAM.
Asynchronous Write signal, MW = 1 to write, 0 to not write, i.e. re

Thank You,

I'm pretty sure there aren't any production FPGAs (not obsoleted) that support asynchronous RAM. If you want a RAM/ROM your two choices are instantiate a RAM core from the vendors IP core generation tool or infer it with behavioral code that follows the vendors template.

If you need the RAM/ROM code to be portable...good luck with that...you're definitely going to be limited in what your RAM features are.