Is it possible to design and simulate a 1 Kbit SRAM array in HSPICE, I mean without connecting each cell manually, is there a function or something else to achieve this in a short way??
Some simulator like hsim will give you the ability to specify the simulation accuracy and speed on different blocks inside RAM. So you can trade-off the simulation time and accuracy as you like. Sometimes, to reduce the simulation time we will remove the parasitic capacitance manually for functionality check only.