module rw_ram ( A ,
I ,
IW ,
RA ,
CKIW,
CKRA,
CEIW,
CERA ) ;
parameter DATA_WIDTH = 44,
ADDRESS_WIDTH = 2 ;
input wire CKIW, CKRA ;//clocks
input wire CEIW, CERA ;//enables
input wire [DATA_WIDTH - 1:0] I ;//data in
input wire [ADDRESS_WIDTH - 1:0] IW, RA ;//addresses
output reg [DATA_WIDTH - 1:0] A ;//read data
reg [2**ADDRESS_WIDTH*DATA_WIDTH - 1:0] mem;
always @(posedge CKIW)
if ( ~CEIW )
mem[IW*DATA_WIDTH +: DATA_WIDTH] <= I ;
always @(posedge CKRA)
if ( ~CERA )
A <= mem[RA*DATA_WIDTH +: DATA_WIDTH] ;
endmodule