RAM/FF inferrention in ISE. Why not RAM?

reg		[31:0] 	ct_tab_start_next_n		[7:0];

always@(posedgeCLK)											
	      if (ag_start)                ct_tab_start_next_n [ct_dev_num]<= ag_secend_n;					
	 else if (ag_go_to_next_block_addr)ct_tab_start_next_n [ct_dev_num]	<= ag_start_block_n_addr;
	 else if (ag_go_to_next_block_n)   ct_tab_start_next_n [ct_dev_num]	<= ag_next_n;
	 else if (ag_go_to_next_block_m)   ct_tab_start_next_n [ct_dev_num]	<= ag_next_m;

INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <ct_tab_start_next_n>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review th...

//------------------------------------------------------------------------------- 
wire		ct_tab_slv_activ_enable	=
			(!ep_enable							)||
			(msr_state == MSR_CNC_SLV			)||
			(msr_state == MSR_DISCNC_SLV		)||
			(slv_state == SLV_CNC				);
wire		ct_tab_slv_activ_data	=
			(!ep_enable							)?1'h0							:
			(msr_state == MSR_CNC_SLV			)?1'b1							: 		MSR_BIND_REQ
			(msr_state == MSR_DISCNC_SLV		)?1'b0							: 		
			(slv_state == SLV_CNC				)?((slv0_ans)? 1'b1 : 1'b0)		:1'b0; 	
wire [2:0]	ct_tab_slv_activ_number	=
			(!ep_enable							)?start_cnt						:
			(msr_state == MSR_CNC_SLV			)?ct_tab_first_slv_free			: 		
			(msr_state == MSR_DISCNC_SLV		)?slv_bind_dev_num				: 		
			(slv_state == SLV_CNC				)?slv_dev_num					:slv_dev_num; 	

always@(posedge CLK)
 if(ct_tab_slv_activ_enable)	ct_tab_slv_activ[ct_tab_slv_activ_number]	<=	ct_tab_slv_activ_data;