Binome
Full Member level 3
- Joined
- Nov 16, 2009
- Messages
- 152
- Helped
- 2
- Reputation
- 4
- Reaction score
- 2
- Trophy points
- 1,298
- Location
- Lyon, France
- Activity points
- 2,405
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_mem is
generic (
data_size : integer:=12;
address_size : integer:=2
);
port(
clock : in std_logic;
enable_write : in std_logic;
address : in std_logic_vector (address_size-1 downto 0);
data_in : in std_logic_vector(data_size-1 downto 0);
data_out : out std_logic_vector(data_size-1 downto 0)
);
end ram_mem;
architecture RTL of ram_mem is
type data_ram is array (0 to 2**address_size-1) of std_logic_vector(data_size-1 downto 0);
signal signal_ram : data_ram := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
if (enable_write = '1') then
data_out <= signal_ram(to_integer(unsigned(address)));
signal_ram(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
end RTL;
signal signal_ram : data_ram := (others => (others => '0'));
data_out <= signal_ram(to_integer(unsigned(address)));
signal_ram(to_integer(unsigned(address))) <= data_in;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_mem is
generic (
data_size : integer:=12;
address_size : integer:=2
);
port(
clock : in std_logic;
enable_write : in std_logic;
address : in std_logic_vector (address_size-1 downto 0);
data_in : in std_logic_vector(data_size-1 downto 0);
data_out : out std_logic_vector(data_size-1 downto 0)
);
end ram_mem;
architecture RTL of ram_mem is
type data_ram is array (0 to 2**address_size-1) of std_logic_vector(data_size-1 downto 0);
signal signal_ram : data_ram := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
data_out <= signal_ram(to_integer(unsigned(address)));
if (enable_write = '1') then
signal_ram(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_mem is
end tb_mem;
architecture test of tb_mem is
component ram_mem is
generic(
data_size : integer := 12;
address_size : integer := 2
);
port(
clock : in std_logic;
enable_write : in std_logic;
address : in std_logic_vector (address_size-1 downto 0);
data_in : in std_logic_vector(data_size-1 downto 0);
data_out : out std_logic_vector(data_size-1 downto 0)
);
end component ram_mem;
signal s_clock: std_logic := '0';
signal s_enable_write : std_logic := '0';
signal s_data_in : std_logic_vector(11 downto 0) := (others => '0');
signal s_data_out : std_logic_vector(11 downto 0) := (others => '0');
signal s_address : std_logic_vector (1 downto 0);
begin
comp : ram_mem
generic map(
data_size => 12, -- pixel size
address_size => 2 -- row size
)
port map(
clock => s_clock,
enable_write => s_enable_write,
address => s_address,
data_in => s_data_in,
data_out => s_data_out
);
clock : process
begin
wait for 1 ns;
s_clock <= not s_clock;
end process;
start : process
begin
wait for 8 ns;
s_enable_write <= not s_enable_write;
wait;
end process;
test_vectors : process
begin
wait for 14 ns;
for i in 0 to 15 loop
s_address <= std_logic_vector(to_unsigned(15-i, 2));
s_data_in <= std_logic_vector(to_unsigned(15-i, 12));
wait for 8 ns;
end loop;
wait;
end process;
end test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_mem is
end tb_mem;
architecture test of tb_mem is
component ram_mem is
generic(
data_size : integer := 12;
address_size : integer := 2
);
port(
clock : in std_logic;
enable_write : in std_logic;
address : in std_logic_vector (address_size-1 downto 0);
data_in : in std_logic_vector(data_size-1 downto 0);
data_out : out std_logic_vector(data_size-1 downto 0)
);
end component ram_mem;
signal s_clock: std_logic := '0';
signal s_enable_write : std_logic := '0';
signal s_data_in : std_logic_vector(11 downto 0) := (others => '0');
signal s_data_out : std_logic_vector(11 downto 0) := (others => '0');
signal s_address : std_logic_vector (1 downto 0);
begin
comp : ram_mem
generic map(
data_size => 12, -- pixel size
address_size => 2 -- row size
)
port map(
clock => s_clock,
enable_write => s_enable_write,
address => s_address,
data_in => s_data_in,
data_out => s_data_out
);
clock : process
begin
wait for 1 ns;
s_clock <= not s_clock;
end process;
start : process
begin
wait for 8 ns;
s_enable_write <= not s_enable_write;
wait;
end process;
test_vectors : process
begin
wait for 14 ns;
wait until s_clock'event and s_clock = '1';
for i in 0 to 15 loop
s_address <= std_logic_vector(to_unsigned(15-i, 2));
s_data_in <= std_logic_vector(to_unsigned(15-i, 12));
wait for 8 ns;
wait until s_clock'event and s_clock = '1';
end loop;
wait;
end process;
end test;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 process(clock) begin if rising_edge(clock) then data_out <= signal_ram(to_integer(unsigned(address))); if (enable_write = '1') then signal_ram(to_integer(unsigned(address))) <= data_in; end if; end if; end process;
Code Verilog - [expand] 1 2 3 4 5 6 7 data_out <= signal_ram(to_integer(unsigned(address))); if rising_edge(clock) then if (enable_write = '1') then signal_ram(to_integer(unsigned(address))) <= data_in; end if; end if;
process(clock)
begin
if rising_edge(clock) then
data_out <= signal_ram(to_integer(unsigned(address)));
if (enable_write = '1') then
signal_ram(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
Clearly, you don't understand what changes in the hardware with this change in code. Nothing at all ! You got to visualize the component that's created with the statements you write in the code.
Whatever is you testbench, you cannot expect the data_out to be visible in the same clock cycle you drive data_in.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?