Qustion about Calibre DRC error which is related to the corner of the area of layout

[mamadmn]

There is an error in Calibre DRC
It says that I should not have any device in the corner of area... Then I think I should use a layer to define the area of layout. But I don't know which layer I can/should use?


Thank you

 

[erikl]

Usually the corner area is already defined by the DRC rules. Check them!

 

[mamadmn]

Hello,
Thank you
I have several errors like DOD.En.2(xxxxx.En.1 for all metals too) which is "enclosure by chip edge >= 0.6" ..... Then I don't know how to define the chip edge or use a special layer.
Thanks

 

[DharmaSlice]

Can you define chip edge by the layer prBoundary.

Or if unsure load layoutXL (if cadence is used) and let it define your chip edge.