LIBRARY IEEE ;
Use ieee.std_logic_1164.all;
Entity BUFF is
Port ( sel, reset, clock: in std_logic; D : in std_logic_vector (3 downto 0);
Zout : out std_logic_vector (3 downto ));
End,
Architecture behave of BUFF is
Signal Q : std_logic_vector( 3 downto 0);
Begin
Process( sel,reset.clock,D)
Begin
If reset = ‘1’ then Q<=(others => ‘0’);
elsif clock = ‘1’ and clock”event then
Q <= D;
end if;
if sel = ‘1’ then
Zout<= Q ;
else
Zout<= “ZZZZ”;
end if ;
end process;
end architecture behave;
Process(reset,clock,sel,Q,D)
Begin
If reset = '1' then
Q<=(others => '0');
elsif(clock = '1' and clock'event) then
Q <= D;
if sel = '1' then
Zout<= Q ;
else
Zout<= "ZZZZ";
end if;
end if;
end process;
if SEL = '1' then
Z <= A + B;
else
Z <= A + C;
end if;
varaible B_ip : whetever_type_b_is;
if sel = '1' then
B_ip := B;
else
B_ip := C;
end if;
Z <= A + B_ip;
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