[SOLVED] Quick VHDL coding question

[Digit0001]

Hi
My question is:

What is the difference (if any) between the declaration of a variable in a subprogram and the declaration of a variable in a process?

Now i believe that there is no difference because the varaible will still be updated immendiately in both cases. However i am not sure and i hope someone can clarify this for me.

P.S

 

[Sckoarn]

Digit0001,
One difference is that a variable in a subprogram will NOT hold it's value, from call to call, where a variable in a process will, from event to event.

That is the only difference I can think of.

Sckoarn

 

[Digit0001]

when you say it does "not hold the value", do you mean the variable will be updated when it reaches the end of the subprogram but not within the subprogram?

 

[permute]

if you have code like below insides of a process:

x <= my_var;
my_var := y;
z <= my_var;

then after cycle 1, x is unknown, and z is y. after cycle 2, x is the previous value of y, and z is the current value of y.

in a procedure, this would not happen. the result of the process would be that x is unknown, and z is y. if the proceedure is run several times, the result is the same -- x unknown, z is y.

 

[Sckoarn]

Digit0001,
Remember that variables are updated at the time they are assigned, even if they are contained in a process.

What permute said is correct. Because when you re-enter the procedure, the value that was assigned to x will have been lost. This will happen to procedures that are defined in a package. If the procedure is defined within a process, then it is in a process, and will hold it's value.

I guess in software'ish terms the life of a variable is limited to the time spent in a procedure, where as a process always exists, therefore it's life of a variable, in a process, is as long as the process exists.

Sckoarn

 

[Digit0001]

thanks for the clarification, i understand now.

 

[Digit0001]

Ok i have another question:

When the following VHDL model of a a device is simulated, it is found that the wrong input may be selected. Explain why and show in two ways how the correct behaviour can be modelled.

	LIBRARY IEEE ;
	Use ieee.std_logic_1164.all;
	Entity BUFF is
		Port ( sel, reset, clock: in std_logic; D : in std_logic_vector (3 downto 0);
			Zout : out std_logic_vector (3 downto ));
End, 


Architecture behave of BUFF is
	Signal Q : std_logic_vector( 3 downto 0);
Begin
Process( sel,reset.clock,D)
Begin
	If reset = ‘1’ then Q<=(others => ‘0’);
elsif clock = ‘1’ and clock”event  then 
Q <= D;
end if;
if sel = ‘1’ then
		Zout<= Q ;
		 else
		Zout<= “ZZZZ”;
end if ;
end process;
end architecture behave;

Can someone find anything wrong with this? The only thing i found incorrect was that it required the Q in the sensitivity list.

 

[TrickyDicky]

Clocked and unclocked logic shouldnt really be in the same process.

 

[Digit0001]

ok, but would something like this still work even if i had one process

Process(reset,clock,sel,Q,D)
Begin
	If reset = '1' then
		Q<=(others => '0');
	elsif(clock = '1' and clock'event) then 
		Q <= D;
	     if sel = '1' then
	        Zout<= Q ;
             else
		Zout<= "ZZZZ";
	     end if;
       end if;
end process;

 

[TrickyDicky]

Yes, as its all inside the clock branch. But this isnt the same code as above, as the output is now registered (in the origional code, Zout isnt registered)

 

[Digit0001]

Yes but isn't that what the question is asking to model the code to make it work without any of the simulation error.

 

[TrickyDicky]

If you simulated the origional code, apart from Q not being in the sensitivity list, there would be no errors. You might have problems with synthesis though.

You dont show what the code is meant to simulate, so I cant tell if the code matches the model.

 

[Digit0001]

So i the first method would separate the clocked and unclocked into different process, however what would be the second method?

 

[Digit0001]

Can someone give me some suggestions on how would i rewrite the following code to give me one adder rather than two adders.

if SEL = '1' then
Z <= A + B;
else
Z <= A + C;
end if;

 

[TrickyDicky]

varaible B_ip : whetever_type_b_is;

if sel = '1' then
  B_ip := B;
else
  B_ip := C;
end if;

Z <= A + B_ip;

 

[Digit0001]

The following question having trouble with:
A signal q is defined via the data type ROM which is defined as
TYPE ROM is array(0 to 15) of std_logic_vector(63 downto 0);
Signal q: ROM;
Write an efficient VHDL code to clear the signal q.

 

[TrickyDicky]

I'm troubled by that question too, because you can't clear a Rom.

 

[permute]

do you mean like
signal q : rom := (others => x"0000000000000000");
or
signal q : rom := (others => (others => '0'));

which initializes the rom to all 0's. that's as close as you can get to doing any changes to a _rom_.

 

[Digit0001]

yeh i think so. unfortunately i don't have any answers to this question so i cannot check if it is correct.

 

[FvM]

I agree, that initializing the ROM is the only meaningful answer to this vague question, and it has been given clearly.

By the way, I think it's a bad habbit to use a thread as a personal blog, adding unrelated questions as they come. (We have some more of these :sad: ). You should better close the thread.