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questions on the hysterisis comparator

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John Xu

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hysterisis comparator

hi,
We desiged a hysterisis comparator with 0.25um TSMC process. The target hysterisis of comparayor is 17mV.The circuit utilized is the well known topology as attached. The silicon test results on hysterisis is as below:
********
VTRP+ VTRP-
sample 1 0.906 0.898
sample 2 0.906 0.898
********
The refernce level is 0.9mv. From the results, we can see that its hysterisis is only 8mv and the obvious unsysmetry for the two trip points. We doubt that the mismatch caused it. But we have used the centroid technique in layout for those paired device and also you can see that we used large size to improve matching. Then why so serious performance degradation? This comparator is a key part in our system. So the accuarcy is important for us.

Would you give us some advice on this issue?

Thanks in adavnce
 

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Davood Amerion

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comparator hysterisis

I think if you increase (W/L) of M6, M7; hystersis increased.
and it may better to increase (W/L) of current source transistor (M5) too.
 

vbhupendra

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tricky questions on comparator

may be reduce input trasistors ! increase M6,7 ! increase tail current (if possible)
 

sunjiao3

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comparator with hysterisis

Dear Davood Amerion and vbhupendra, it seems that you are talking different topics from what John Xu told. You are talking about the effect that will affect the hysteresis width. Not the possible answer for the phenomen John mentioned.
As for me, it must be caused by some mismatch. I am sure that mismatch can be allevated rather than eliminated when common centroid structure. But, how big is the allevated mismatch? I am not so sure. Maybe someone could give a rule of thumb.
 

OpAmp

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Hi guys,

I'm agreed with sunjiao3. It is because of mismatch. Even if you use common centroid methods and increase the area of transistors to get better mathing, a mismatch of about a few mV is expectable in CMOS technology. I mean, even if you use the best matching methods, a mismatch about a few mV (<10mV) is possible. So getting a hysterisis of 17mV with the configuration is, in my view, impossible.
 

    John Xu

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John Xu

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OpAmp said:
Hi guys,

I'm agreed with sunjiao3. It is because of mismatch. Even if you use common centroid methods and increase the area of transistors to get better mathing, a mismatch of about a few mV is expectable in CMOS technology. I mean, even if you use the best matching methods, a mismatch about a few mV (<10mV) is possible. So getting a hysterisis of 17mV with the configuration is, in my view, impossible.
Thanks for the reply. Is there any configurations which have better matching characteristics for hysterisis comparator?

thanks
 

leebluer

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hi, OpAmp,

I have some confused about your saying.

'So getting a hysterisis of 17mV with the configuration is, in my view, impossible.'

Do you mean that because the Voffset in CMOS technology is about 10mV or so, the comparator with a hysterisis of 17mV isn't reasonable. Perhaps we should design a comparator with more hysterisis?
 

sunjiao3

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leebluer, I think so. Not only because the vos, but also the width of the hysteresis window will vary with mismatch. So, increase the hysteresis width will alleviate the effect of mismatch in some way. I've read some paper about allevating the mismatch effect on compaper. The best one got a variation of 1mv from the center.
 

OpAmp

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Hi,

I am not sure that if the design of a hysterisis of 17mV is in possible. As a solution, you can use an operational amplifier with correlated-double sampling (for eliminating the offset of the amplifier) to amplify your signal and then use a comparator with hysterisis of about 100mV or more (depending on the gain of the CDS amplifier).
You may try to find a comparator with hysterisis of 17mV, but I’m not sure if you will succeed.
Once, I needed a comparator with hysterisis of about 50mV. But when I simulated different structures in process corners and , I decided to change my system design in order to not needing a comparator with 50mV hysterisis.
 

    John Xu

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