Questions on jitter modeling in bang-bang CDR(Clock Data Recovery) circuits

Status
Not open for further replies.
T

teem

Junior Member level 1
Joined
Nov 17, 2009
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,408
Hi,

Attached is paper from IEEE talking about jitter modeling in bang-bang CDR circuits. I am quite confused with the comments from authors and do not understand how to come out equation(1) and equation(3). Could any experts explain these 2 equations in detail?

Thanks very much in advance.
 

Attachments

  • Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits.pdf
    1 MB · Views: 53

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…