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Questions on jitter modeling in bang-bang CDR(Clock Data Recovery) circuits

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teem

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Hi,

Attached is paper from IEEE talking about jitter modeling in bang-bang CDR circuits. I am quite confused with the comments from authors and do not understand how to come out equation(1) and equation(3). Could any experts explain these 2 equations in detail?

Thanks very much in advance.
 

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  • Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits.pdf
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