Questions on Fanout of 4

promach · Feb 13, 2018

After some math, it can be shown that the minimum delay is achieved when the load is driven by a chain of N inverters, each successive inverter ~4x larger than the previous; N ~ log4(Cload/Cin)
In the absence of parasitic capacitances (drain diffusion capacitance and wire capacitance), the result is "a fan out of e" (now N ~ ln(Cload/Cin))

For https://en.wikipedia.org/wiki/FO4 , could anyone help to derive the above two equations under different conditions ?

ThisIsNotSam · Feb 13, 2018

promach said:
For https://en.wikipedia.org/wiki/FO4 , could anyone help to derive the above two equations under different conditions ?

define 'different conditions'. if the load is changing the equations are exactly the same. you would need a process that is really different from CMOS to effectively need different equations/assumptions.

Questions on Fanout of 4

promach

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ThisIsNotSam

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Questions on Fanout of 4

promach

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ThisIsNotSam

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