# Questions on compensation for DC-DC buck converter

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#### wholx

##### Member level 4 schema buck converter

i'm doing a study on the compensation for DC-DC buck converters.

the schema without compensation shown in the attached pic will ocillate as expected. so, some resistors and capacitors were added into the circuit to stabilize the output. in this case, those were R43, C4, C3, R44, C5 as shown in the other picture. If the specs are listed as followed, how can we then decide the value of R3, R4 and then R43, C4, R44 and C5?

specs:
regulation of output voltage Vs to 3.3V as Vbat varies from 6V to 24V and Rcharge 6ohms. the external components are L1=22uH, C1=10uF with an ESR varies from 1mOhms to 10mOhms. the circuit should be stable as Rcharge varies from 6Ohms to 1kOhms.

some hints about the case before compensation:
1. one pole at 1/sqrt(L1*C1)
2. one zero at 1/ESR*C1, where ESR is the equivalent series resistance of output capacitance

some hints about the case after compensation:
1. C3 adds a 0 pole to the circuit as an integrator.
2. R2, C1 make one zero at 1/(R2*C1), R1, R3, C3 make another zero at 1/(R1+R3)*C3
3. two poles are at higher freq to get the expected phase margin, one at 1/R3*C3, another at 1/R2*C2

i've tries to calculate the parameters according to the specs, but i got some problems:
1. how to make sure the output is 3.3V? it seems the output value relates to R4, though i haven't figured out in which way

2. how to decide the dc gain or the unity gain bandwidth?

3. i made some calculations by placing the two compensation zeros around the 1/squr(L1*C1) by a factor of 3.3 each. it seems this work but i dont know why

4. how to figure out the phase margin?

5. is it possible to simulate the open loop gain with spice by breaking the loop? if yes, how?

thx a lot for your help! any information is welcome.

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