I'm a newer of analog IC design, I want to do some research of pipeline ADC. who can give me some advices, system analysis(and design) and trade-off between modules are much better. Thank you very much.
You can search in the internet using google. Ther's alot of references on pipelined ADC. I think the current state-of-the-art is using 1.5 bit per stage at few hundreds mega sample per second (MSPS). Also you need to familiar with ADC characteristics such as INL, DNL, Gain Error, Offset Error, SFDR atc and how to model those using system level simulator such as MATLAB Simulink. I recommend you to read thesis report by ABO from UC Berkeley. Its very good!