I never use verilogA or VHDL_AMS for real design ,
I ever use matlab for analog behavior ,
but for Mix mode SOC design ,
in gerneal , analog block design by analog RD , digital is by digital RD ,
project leader simulation whole chip by hsim/nanosim , but
none use beahvior sim in Top level as I know .
like Saber , Dolphin smash .. support analog + digital design ,
but project leader only use "hsim or powerMill" tool .
Have any fabless design use RTL_a ? I don't know .