Questions and problems about LDO design

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ilter

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Dear all,
I want to design a LDO. How do I let my load current is bigger?
Let error op's gain larger or power mos's size large?
How do I do? If you have some document, please let me know.
My supply is 1.8V and output voltage is 1.5V.
But I run spectre , I have a question.
If my load current is 50mA , my dc output voltage is sometime 1.8V and 1.5V
I am very confused. If I use ideal resistor , I don't have this question.
Thanks.
 

Re: LDO question

download the PhD thesis of Rincon mora from following link
**broken link removed**
 

Re: LDO question

You can download it from.
 

Re: LDO question


Dear all,
I have a question. I simulate my LDO.
I find my line regulation is negative.
Do you think why? Thanks.
 

Re: LDO question


Hello,
I design my LDO. My input voltage is 1.8V and output voltage is 1.5V.
I find my simulation is in FF , high temperature and high voltage of 2V(input voltage). My output will be 1.78V and not 1.5V. I don't know what's wrong.
I think my error amp's gain is not large? or others reasons.Thanks.
 

LDO question

hi ilter,

We have to increase the size of power pmos to increase the ability of driving. As to your case, that is, sometimes 1.8v or 1.5v, and it should be due to the small size of the power pmos. It must be in the linear region while output is 1.8v.

thanks
arsenal
 

LDO question

for the 2nd issue. the resistors will be proportion,maybe you simulated the LDO with BandGap. The output voltage of the bandgap change, so the LDO's output will be changed
 

LDO question

you have to have a right combination of your feedback voltage divider resistor to get the 1.5V output at 1.2V reference.

Vo = 1.2V[1+(Rf/R1)]

When estimating FET's capability you can compute FET's power at load current.

P = (Vin-Vout)*Iload

Added after 1 minutes:

Also, don't forget to put a filter caps at the output to have output stability (reduce voltage ripple)
 

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