Hi all,
Please who can reply to these 2 questions:
1- For a 65 nm tech (Power supply of 1 V) I obtained spikes of 0.2V. Generally speaking, for a given power supply from which percentage we consider spikes dangerous to our circuits ?
2- For a gate, Spikes in the output can be reduced by increasing the Fall/rise time of the input signals. I don't like this solution coz it require decreasing the frequency. Does anybody know another solutions ?
Thanks in advance for your time.
Regards,