The PLL implements a full-rate architecture because of its structural simplicity and operational robustness with regard to various data patterns. Compared with half-rate architectures [6], full-rate CDR requires higher circuit speed [7]. On the other hand, half-rate designs require high-speed multiphase clocks (or data) that need to be very well matched to avoid degradation in jitter tolerance. As a result, in full-rate CDR, the design of the voltage-controlled oscillator (VCO) is simplified and the physical layout of CDR can be very dense to minimize parasitics, which in turn helps to improve speed and reduce noise coupling.
In addition, the full-rate CDR generates a low jitter full-rate clock which is applied to a separate flip-flop to retime the data from the input amplifier.