dhzpdl13
Newbie
Hello,
I have a few questions about PCIe specification.
As I don't have the PCIe specifications at hand but from PCI Express Base Specification Revision 6.0,
1. What do you think .. which conditions or states let directors make the specification below?
- For the common receiver parameters, mininum input impedance of receiver should be 1.0K ohm at least when DC input CM for V<0 during Reset or power-down. (Z_RX-HIGH-IMP-DC-NEG)
- Note 4 let me think that this specification matters for receiver detect circuits of transmitter, but there is no obvious wording or evidence about it.
2. When designing T-coil in both receiver and transmitter, 3-dB bandwidth in terms of AC gain suffers especially in receiver.
I think it is inevitable to have low 3-dB bandwidth especially in receiver because of high parasitic capacitances from esd-protection diodes and receiver input.
I also think that the design of T-coil should be focused on the improvement of return loss by priority, I'm curious about other people's opinions.
I have a few questions about PCIe specification.
As I don't have the PCIe specifications at hand but from PCI Express Base Specification Revision 6.0,
1. What do you think .. which conditions or states let directors make the specification below?
- For the common receiver parameters, mininum input impedance of receiver should be 1.0K ohm at least when DC input CM for V<0 during Reset or power-down. (Z_RX-HIGH-IMP-DC-NEG)
- Note 4 let me think that this specification matters for receiver detect circuits of transmitter, but there is no obvious wording or evidence about it.
2. When designing T-coil in both receiver and transmitter, 3-dB bandwidth in terms of AC gain suffers especially in receiver.
I think it is inevitable to have low 3-dB bandwidth especially in receiver because of high parasitic capacitances from esd-protection diodes and receiver input.
I also think that the design of T-coil should be focused on the improvement of return loss by priority, I'm curious about other people's opinions.