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Questions about FPGA clocking

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Member level 5
Sep 26, 2001
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Hi all,

I'm sure not to be the first guy running into this problem, so I need some advice from all the guru's out there :wink:

My concrete question is about clocking signals on FPGAs. I know that there are (a very limited number of) dedicated clock inputs available and that those should be used first. But what happens if I have some further clocks that should be used for a sub-circuit in the FPGA? May I use any other pin configured as input pin?
How should low frequency clocks be dealt with? Should they be generally synchronized to the other higher frequency clocks?
Finally, there is just one further question: if I downscale a high-frequency clock to some lower frequency by using a simple counter (MSB of the counter is the "output" clock) and feed some other logic with this signal, I can find in the report window this signal as addditional clock signal. Since gated clocks isn't a good practice, how are problems like this dealt with??
Thanks for any good advice,

what is the purpose of dll in fpgas

Dear friend,
Can I have more than eight clocks on a FPGA which has only 8 dedicated clock pins? The answer is yes, Obviously with one important condition : there should not be a heavy load on your clock signal, or you should do some clock synchronization for transferring data from this clock domain to chip's main clock domains.
It is a very bad idea to use a counter for making lower frequency clock pulses from a high freq. clock. Instead use Clock DLL ( Or DCM in V2 designs. ) The clock DLL will easily make a freq. devided, phase compensated version of your main clock for use in your logic.

fpga clocking

i think that is a milestone the frequency of your clock, in new devices if you use a low clock there is no problem you can have how many clock you like.the clock input pins are dedicated to drive the longline to have skew zero to all flip flops,but in a FPGA you can also use all pins to clock.

external dedicated clocks for fpga

As mami_hacky said the best solution is to use PLL, DLL or DCM. If you don’t have these precious resources, you can also use counters, but the output should be used as clock enable for the rest of FFs that you want to clock with a lower frequency. It’s a good design practice not to load very heavy this CE signal, otherwise you might experience unpleasant issues. Sometimes you will need to replicate the CE signal in order to have an acceptable loading. Don’t forget to declare all these paths as multicyles.

dll fpga

could someone simply add buffers at the clock to help with the loading?

clock_dedicated_route ucf example

Hi all,

thanks for your good and fast replies. I'm using the Spartan II (2S200) which has some DLLs, all dedicated input clock-pins are already consumed and the required frequency for my application is much lower (lower than the highest division ratio available from the DLL) than the lowest frequency of the other clocks.
Anyway, it's fine if I can use the MSB output as CE. Since I'm quite unexperienced with I$E 5.1i, could someone (maybe aalbu?) please explain me how to declare this path as a multicycle path??
Thanks for all your help,

fpga synchronize to lower clock

Hi Maddin,

it's not only the frequency that matters: if the clock skew of the non-dedicated clock net exceeds the routing delays between flipflops clocked on that clock, you also get big problems (new data arriving before the old clock edge was processed).

So you can either route the non-dedicated pin to dedicated clock buffers (BUFG) if you still have some spare ones. This way you only lose some propagation delay between external clock pin and internal global clock net. The dedicated clock pins have much lower delay, obviously.

Alternatively, you can route the clock using standard nets (non-dedicated clock net) but then you should use a MAXSKEW constraint (look it up in the Xilinx Libraries Guide) to avoid trouble.

counter using non clock net

you can use any pin to clock your circuit, the warning is because you have more delay in your signal when you use any combinatory logic to control your signal,
to sincronise your clocks you can use any pll circuit on altera fpgas and an dll on xilinx fpgas
good look and sorry about my poor enghish

fpga clocking


thanks anybody who has contributed to my inquiry. I got my design to run and now it't time to switch from drinking coffee to some other drink :lol:

Short comment to snake:
It doesn't matter how good anybodys ability to communicate in english is as long we all can imagine what "the guy on the other end" wants to tell us (I think this is true for anybody else out there too). However, your skills are, as I can see, absolutely ok.


how to use maxskew constraint

I have a low end FPGA which has no PLL or DLL.
Is it possible just to use digital gate to implement DLL function ?
Is DLL all digital circuit ?

dcm dll low freq clock sync

2 rtl2gdsii
1. There are several "pseudohobbist" sircuits on two flip-flops for doubling clock - but IMHO it no good way - not stable work in some condition...

2. DLL is not full digital circuits - it work like PLL

fpga non clock pin

I am assuming you have one external clock coming in, and you are dividing that clock to get slow clocks. As others have mentioned, you should always have only one clock. And instead of the slow clocks, use the CE.

If DLLs don't do the job for your clock division, you can use SRL16E to do that job. THese are very neat. Every LUT in Virtex/SpartanII can be configured as a SRL16E primitive. And you can efficiently implement your clock division using SRL16E instead of counters.

1 SRL16E - 1 LUT - you can get clk/16.

You can look at this page for more information on SRL16E here.
**broken link removed**

Hope this helps,

Kode, thank you very much for the useful hint.

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