easytarget
Member level 1
Questions on CDR
Hi,
I have to design a CDR and I have a few questions, I would appreciate your help.
1st one (simple): I'm thinking about using an LC VCO, so how can I plot the capacitance vs. vcontrol, you know like the image attached, using hspice or preferably cadence. Thanks.
Edit: oops, I don't know why I can't attach the image, but it's that curve that shows the depletion and then inversion region as the gate voltage increases in an nmos, you know it
Hi,
I have to design a CDR and I have a few questions, I would appreciate your help.
1st one (simple): I'm thinking about using an LC VCO, so how can I plot the capacitance vs. vcontrol, you know like the image attached, using hspice or preferably cadence. Thanks.
Edit: oops, I don't know why I can't attach the image, but it's that curve that shows the depletion and then inversion region as the gate voltage increases in an nmos, you know it