Questions about 1.5bits/stage in pipeline ADC

noviceca said:

I'm trying to implement a 10-bit 20MS/s pipeline ADC in 0.25um CMOS technology. In designing 1.5bits/stage, I have two questions:

1. In switched-capacitor sample-and-hold circuit, I use CMOS transmission gate to implement switch. Usually NMOS and PMOS have same size or different size? For C=1pF, which size is better, 5/0.25 or 50/0.25?

The switch size should be large enough to make sure that the switch can set in the required resolution in the switch on clock period. Normally PMOS should be 2~3 times of NMOS transistor size

2. I use switched-capacitor circuit to implement multiply by 2.Should I get exactly gain of 2 or it is impossible to get exactly gain of 2 due to finite gain of opamp? How close to 2 is enough? Is it 1.94 OK?
the gain error should be smaller than 1LSB
Thanks for any reply!

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noviceca said:

I'm trying to implement a 10-bit 20MS/s pipeline ADC in 0.25um CMOS technology. In designing 1.5bits/stage, I have two questions:

1. In switched-capacitor sample-and-hold circuit, I use CMOS transmission gate to implement switch. Usually NMOS and PMOS have same size or different size? For C=1pF, which size is better, 5/0.25 or 50/0.25?

2. I use switched-capacitor circuit to implement multiply by 2.Should I get exactly gain of 2 or it is impossible to get exactly gain of 2 due to finite gain of opamp? How close to 2 is enough? Is it 1.94 OK?

Thanks for any reply!

Click to expand...