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question regarding usage of Generic in VHDL

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habbas33

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hi

I am little confused regarding the generic usage in vhdl... I am trying to understand some reference code and I found this...

Code:
generic (
    APPDATA_WIDTH : integer := 64
    );

port (
    clk0,rst0 :in std_logic;
    rd_data_out  : out  std_logic_vector(APPDATA_WIDTH-1 downto 0);
    wr_data_in      : in    std_logic_vector(APPDATA_WIDTH -1 downto 0);
);

in_sel_proc : process(clk0,rst0)
begin
   if (rst0 = '1') then
     ...
   elsif(clk0= '1' and clk0'event) then
   rd_data_out <=wr_data_in(127 downto 1) & '0'; -- this wr_data_in is declared 128 bit in outside module from where it is given as an input    
 end if;

my confusion is that if data width assigned using generic (appdata_width) is 64 bit, how we can assign 128 bit data to the bus.
the code is synthesizeable and implementable and does not show any error.
 

sharath666

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If datawidth is 64, then you can assign only 64 bits to the bus.
If you want to assign 128 bits, then change the generic value to 128.
 

habbas33

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yeah but this is not my code and it is working for 128 bit. I am not sure why that is the reason I put the question...
 

TrickyDicky

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It looks like the designer added a generic, and then chose to ignore that generic in the code.

ie. a bug

If you set the generic to anything other than 128 it will not compile due to width missmatches.
 

std_match

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my confusion is that if data width assigned using generic (appdata_width) is 64 bit, how we can assign 128 bit data to the bus.
the code is synthesizeable and implementable and does not show any error.

The value "64" in the code is only the default value, and as already pointed out, it can't work. The only explanation is that the default value is overridden when the component is instantiated. Look at the instasntiation code, it must set the generic to 128.
 

FvM

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In any case it's an example of bad coding. APPDATA_WIDTH should be used in all places that depend on the actual datawidth of in/out port.
 

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