Question regarding SRAM compilers

[santhosh.vlsi]

Hello all,

Please provide me the details about memory compiler(generator).As per my knowledge compiler generates the cut according to user specifications.What parameters we have to consider in cut generation, like how to consider MUX,WORD,BIT parameters.apart from these three parameters any thing else to consider and how my top level memory look like after generation of layout.

1. Which specific tool used in cadence as memory compiler.
2. Insight on Memory leaf cell
3. what is the role of memory layout/design engineer in the VLSI industry.

Thank you

 

[jbeniston]

Other parameters to consider include, bit/byte write capability, BIST muxes, retention modes, dual or single port.

1. There isn't a Cadence memory compiler. Memory compilers typically come from foundries or IP providers. They generate views that can be used in tools from Cadence.
2. Memory leaf cell? Do you mean the bit cell? Search for 6T SRAM cell.
3. To design memories?