Question regarding RC Compiler - clock_uncertainty

[Arvindh19]

Hi,
I was going through the manual of RC compiler where I came across the command clock_uncertainty . Can someone help me understand as to what it does ( I know the meaning of clock uncertainty but want to know how the command works)
Thanks

 

[rca]

Re: Question regarding RC Compiler

the command add margin on clock, means the period/half period are reduced.

 

[yadavvlsi]

Re: Question regarding RC Compiler

Allows you to specify the expected clock setup or hold uncertainty associated with jitter, skew, and a guard band when performing setup and hold checks for clocks or clock-to-clock transfers. You can specify separate clock uncertainty for setup (-setup) and hold (-hold). RC subtracts the setup uncertainty from the data required time for each applicable path, and adds the hold uncertainty to the data required time for each applicable path.

 

[Arvindh19]

Re: Question regarding RC Compiler

Thank a lot :smile:

 

[englishdogg]

Re: Question regarding RC Compiler

i am sure that it is an attribute and not a command. Also this is specific to RTL COmpiler and doe snot map to standard SDC that we all use.

RTL Compiler also has its own set of commands/attributes for constraints and this is one of that. Just wish to clarify the same.

 

[rahul.achates]

Re: Question regarding RC Compiler

its not attribute .. it is a SDC command which understandable by RC , DC and other synthesis tool .. it's a standard command.

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the full SDC command is set_clock_uncertainty ..

 

[englishdogg]

Re: Question regarding RC Compiler

i am saying in RC its a attribute - made it clear in my append that it is not a SDC.
SDC is what you mention 'set_clock_uncertainty'

RC has its own constraint commands as well and in RC it can be managed using attributes as "clock_*_uncertainty"