When I use worst cases simulation(may also called corner simulation), for example, worst power model, worst speed model, worst one model ,etc....provided by the design kit for my CMOS circuits, I find there are significant differences in the simulation results compared to the typical mean model. and I have no idea why does it happan and how can I optimize the circut to make it not sensitve to worst cases models.
however, does the simulation result from the worst cases realistic, or it is just too pessimistic? how can I make the circuit more robust?
1. first you gotta understand what is the major simulation parameter affected by those corner simulation( such as cox, vth...etc)
2. if you see a big difference between typical and worst case simulation, there is a chance that one of the transistors is biased at the edge of saturation, therefore it is turned off in the worst case.
3. usually the circuit needs to meet the best and worst case simulation to get a high
yield.
Usually the corner, temperature and power supply determine the worst case together. Some parameters of the model, such as Vth, are calculated through formula. So even all of transistors is saturation, the significent difference exists. Perhaps the solution is the special structure.
I wanna quickly mention a number of points:
- A circuit that works in tt doesn't necessarily work as well in corner cases.
- A circuit should be specially designed for corner cases in order to be simulated correctly there.
- I believe (this is a personal belief) that if a circuit works in corner cases, it will work in tt.(please correct me if I am wrong)
So it is no surprise that the circuit isn't working properly.
I don't agree, for example if u are designing an OTA with 7 or 8 specs , Gain,PM,GM,GBW, etc.... u will find that some of those specs will get better in certain corners while others will get worse, and thus to ensure that u cover all the corners in ur design u should determine which corner is the worst corner for each spec and take this into your consideration while designing.