question on using for loop in verilog

[yupina-chan]

hi. i have a question on using for loop.
for example, i have an 'always block' then i use for loop inside like this one:

integer i;
integer count = 0;

reg [7:0] ram [255:0];
initial begin
for (i=0; i<256; i+1)
     ram[i]=0;
end

always @(posedge clk)begin
   count <= count + 1;
   if(count == 5) //condition to restore ram contents
       for (i=0; i<256; i+ 1)
          ram[i]<=0;
   else              // fill ram with 8'b00001011
       for (i=0; i<256; i+ 1)
          ram[i]<=8'b00001011;
end

1. will it take 256 clock cycles for the ram to be filled with 8'b00001011? or it only takes one posedge clk?
2. i initialized my ram with zeros using for loop before the always block. is this the right thing to do, like it can be synthesized well in the real board implementation?
3. also, my process needs to restore the values inside a certain process? can i use for?
3. what's the best way of coding my code above?

 

[mrflibble]

For loops unroll hardware. Think of the for loop as spatial, not temporal.

If you want a C-style for loop where you have 256 distinct points in time where you do some action, then you should use a counter and/or FSM to handle these actions.

The for loop in the initial block is valid, since that can be evaluated at synthesis time. As in, that will translate to hardware with all the ram initial values set to zero.

The for loop in the always @posedge clk block will not synthesize to hardware. May I suggest reading your favorite verilog book on what the for loop can and cannot do.

 

[yupina-chan]

hi. mrfibble, thank you for the information.
i have seen projects that uses the for loop. what are the consequences of using for loop in my implementation?

ok so, i researched on this on the net and decides to write an fsm for my for loop. my next question is, how can i use my fsm in my code? how should i insert this in my always block?

or is there another method in filling all memory contents at the same time in an always block?

ps. my code is not like as simple as the one above

thank you very much

 

[pbernardi]

More that the loop itself, there is another problem: in this code, you are trying to clean a RAM in once cycle. This is not possible in a block RAM or distributed RAM. Therefore, your FPGA will try to infer a RAM with flip-flops, that is the worst way to construct a RAM (uses much logic, it's complex and slow).

Real RAMs has as characteristic have a limited access per clock (one, two or four, depending of the type on Xilinx FPGAs), so you cannot access hundred addresses and attribute a value to them.

If you want to fill the RAM with values, you have to know what is the maximum simultaneous access per clock, and make n access of x bytes during m clock cycles, where m*n*x is the bytes you want to write.

You can initialize the RAM with the values you want, however.

 

[yupina-chan]

thanks pbernardi. now, i know i have been wrong all this time since I've always ignore warnings like this(infer ram) after compilation. i am new to fpga and don't get enough guidance from people in my univ. its like im working on own and a few people. a hardware mindset is what i really needed since i'm most familiar and had more experience with software like C.

can i ask one more question? mrfibble said that the for loop in my initial block can be synthesized. can i, instead of this, use $readmemh/b in initializing the RAM? is this synthesizable?
thank you again.

 

[mrflibble]

can i ask one more question? mrfibble said that the for loop in my initial block can be synthesized. can i, instead of this, use $readmemh/b in initializing the RAM? is this synthesizable?
thank you again.

If you put the $readmem statement inside the initial block, then yes. Anywhere else, no synthesizo senior.

Just a thought, it probably depends on the synthesizer. But at least for xilinx xst it is synthesizable (inside the initial block, obviously).