question on cadence soc

[ragramya]

hi friends,
I have started working on cadence soc encounter. when I am writing code on verilog , no errors will be found when I am doing my synthesis. But when Iam writing a code in VHDL, lot of errors are found when iam doing my RTL synthesis. Is it cadence soc encounter will only work for VERILOG, or VHDL or both.
Ramya

 

[yadavvlsi]

Yes, RTL Compiler supports VHDL & verilog both. What are the Errors you getting?

 

[Nora20]

hi
i think u have problem in synopsys ( generation .sdc and .mapp.v files) your script are on the verilog so in vhdl you have problem