abcyin
Full Member level 4
Hi, all,
I am now involved in a project to design a bluetooth receiver, the GFSK data information could be demodulated with a PLL-based demodulator, and you know, the demodulated signal here is not a rail-to-rail signal, which can not be further processed with the following digital circuits, so, the question is, can I adopt a 1-bit ADC to distinguish the data? have you ever seen such kind of receiver architecture?
or could you anybody suggest me some corresponding documents? Thanks very much.
All the best.
I am now involved in a project to design a bluetooth receiver, the GFSK data information could be demodulated with a PLL-based demodulator, and you know, the demodulated signal here is not a rail-to-rail signal, which can not be further processed with the following digital circuits, so, the question is, can I adopt a 1-bit ADC to distinguish the data? have you ever seen such kind of receiver architecture?
or could you anybody suggest me some corresponding documents? Thanks very much.
All the best.