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question on ADC jssc2006 papers

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totoro

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adc question papers

In "A 10-bit 400-MS/s 160-mW 0.13-m CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration"
the part III said that
On the other hand, the 3 dB frequency during the sampling phase is set to be about ln(2^(N-1)) larger than
during the amplifying phase since signal sampling should be
performed 2^(N-1) times more accurately than signal amplifying.

Why?

And how did the auther get the two f-3db value for sample and amplify phases?
 

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