Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
USB2 PHY will convert 480M -> 30/60M clock (UTMI), but in PHY block
some logic in High speed , like data_receiver ==> 480M (layout carefully & y man ) , and some block convert 480M --> parallel 60M ...
then goto UTMI block
PHY is analog , only UTMI(in PHY) is logic , and you can not find it ..
USB2 design is very expensive .... and it is ver HOT product
you can not get any USB2 PHY circuit or RTL code ...
as I know NEC sold USB host cost $300000 (USA dollars)
very very expensive ..
other Company PHY IP is cheap , but usually have many BUG ..