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# [question] How to double frequency?

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#### etrobin

##### Member level 1
Hi,All,

My system clock is 24Mhz,but my peripheral is 48Mhz, how to double my system clock to 48Mhz? or I just use the system clock 48Mhz,then divide to 24Mhz for other peripheral? Where can I get the info about double frequency? How do u do if u had the problem the same as mine?
have a nice weekend............

Using a 48M clock and dividing it is much easier than clock multiplying. If you do decide to clock multiply, Cypress makes some nice components for doing that sort of thing.

If you want to do it the hardest way possible, you can double a clock by phase shifting it 45 degrees and then XORing it with the pre-shifted clock. Easier said than done.

use phase lock loop (pll) to do this, there
are many way to realize.

search in forum someone has upload book on phase lock loop

Can play with this

clock doubling circuit, to operate at approx 500kHz, using CMOS logic.

+-------+
| hc86 |
+-----------| |
clkin ----+ | +--- clkout = 2*clkin
+-N-R-+-N---+ |
| | |
C +-------+
|
gnd

where N is a NOT gate (hc04?)
R is a 10k resistor
C is a 47pf capacitor.

The circuit functions quite well and is stable. If the Not gates are omitted,
however, it becomes unstable, and gives variable width pulses.

Or use a 74F74 48 MHZ / 2

clk in -> 48 MHZ
!Q -> D
Q -> Output

Hi,
Looh for "push-push" frequency doubler.
It is much simpler that PLL and works even for very high frequency, which can be a problem in GrimReaper's solution.
Regards

Z

By XOR'ing the clock with it's delayed copy (apply the clock dirrectly to the one input of 2 input XOR gate, then apply the same clock via an RC LPF network to the other input of the XOR gate).

Hi Etrobin,

I would build a diode frequency doubler with two diodes + trifilar transformer wound on a small ferrit bead/ or toroidal core, see Fig 2 of the article at h**p://www.noblepub.com/archives2/2000/march2000/mar2000pg82.pdf (* => t). No need for tuning, it is wideband and you can use 1N4148 or similar high-speed switching diodes (or Schottky diodes) selected with a digital multimeter's ohm/diode test function.

You can build it in a few minutes (the number of windings on your core can be 3 times 4-5 turns, trifilarly) and its output at the double frequency can be checked with an oscilloscope at once.
This is similar to Zorro's push-push suggestion, I suppose.

Regards, unkarc

Looks like you have two choices. I like frequency division rather than doubling since you have a lot of options here.

With 48MHz CLK and use master slave flip flop technique as frequency divider to get 24MHz.
Use delay locked loop circuit which is quite common in clock management and distribution technique.

For frequency doubler, there RF technique that uses mixer. Active mixer is preferred since they are normally in IC form. Use 24MHz as input for both RF & LO port and you will get 48MHz IF output.

Hope this helps.

Here is divider

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As others have said, two choices are possible (48 MHz oscil with divider or freq doubler) with second option being a bit more tricky if you need 50% duty cycle.

You could try a simple solution that could give you cca 50%.
Use 74LS86 for EXOR gate and feed it direct 24 MHz on one input and delayed 24 MHz signal on the other input. For delay use another EXOR gate on the same chip, with one input tied to GND or VCC (whatever). Propagation times of LS series could be just right to do the job. LS is also less susceptible to ambient temperature and voltage variation than HC. Solution isn't exactly NASA-certified, but it is a quick h@ck that could work.

For digital circuits, don't use any h@ck-methods, you may just cause interference or glitches.
Best solution is to use a 48MHz system clock, and a 74ls93(ttl) or 40161(cmos) binary counter.
Connect your 48MHz clock as the clock, tie !RST and !Load to +5v, and get 24MHz clock from Q0.
You can also get 12MHz clock from Q1, 6MHz from Q2, and 3MHZ from Q4...

u can try out this simple scheme wherein the propagation delay through a NOT gate is utilized to introduce phase shift in the input clock and which then feeds a two input XOR gate another input of which is fed with undelayed clock signal. u may have to experiment with the number of not gates connected in series to get nearly 50% duty cycle. The layout is in

The problem with signal delaying and NOT and XOR gates is that these type of cicuits tend to not be stable over temperature and can change duty cycle or jitter.
The pll or chip clock doubler solutions are better although of course more expensive and not so readily available.

Hi

Yes , for playing around or protoyping XOR scheme is ok , but for serious design , start at 48 Mhz and devide down. Should be the cheapest solution as well

Willebul

This is what phase lock
loops are good at
ooorrrr just change the
edge triggering then invert it!

These is one of the best:

Check also:

You flash the PLL frequency and you have a clean DSP/CPU clock reference.
G2O

I don't want to repeat what has been already said, so i want to remind you an old-fashioned method like that of TV transmitters: Frequency multipliers.
You take an high frequency transistor, use C class operation: 24Mhz signal on the base and a 48Mhz Filter as collector load.
Although I don't believe it's suited for digital applications.

You can also use CY2308-2 from Cypress/IDT to do the job. No external components required! Has all the things to double the input frequency.
Gopal.

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