[SOLVED] Question: Full rectified waveform related

[win_win]

I have 2 questions below related to the full rectified waveform:

1. How to eliminate the negative cycle of the full rectified waveform?

2. We all know we can use a full bridge rectifier to get the full rectified waveform.
I am curious to know how to do it reversely, i.e., from a full rectified waveform to a sinusoidal one.

Could anyone help to contribute your idea to those questions?
Thanks a lot

WinWin

 

[kappa_am]

Hi'
I am not sure that I have understand your first question, if you mean ripple, use appropriate capacitor regarding to your load.
about second question: you can use an inverter. this is common configuration in variable speed drives. google back-to-back inverter rectifier pair.

 

[win_win]

Sorry folks,

The first question should be corrected as following:
1. How to eliminate the positive cycle of the full rectified waveform.

I have 2 questions below related to the full rectified waveform:

1. How to eliminate one cycle of the full rectified waveform?

2. We all know we can use a full bridge rectifier to get the full rectified waveform.
I am curious to know how to do it reversely, i.e., from a full rectified waveform to a sinusoidal one.

Could anyone help to contribute your idea to those questions?
Thanks a lot

WinWin

- - - Updated - - -

Hi kappa,

I didn't make myself clear for the 1st question.
It should be changed to "how to eliminate the negative cycle of full rectified waveform"

<a title="Full wave rectified.jpg" href="http://obrazki.elektroda.pl/9512404600_1410500150.html"><img src="http://obrazki.elektroda.pl/9512404600_1410500150_thumb.jpg" alt="Full wave rectified.jpg" /></a>

- - - Updated - - -

Hi Kappa and folks,

The full rectified waveform contains both positive and negative cycles, I would like to know if there's a way to
eliminate the negative cycle.

As for the 2nd question, actually my application is, the AC input and its full bridge rectifier are sparated from the power supply, located somewhere else. (It is a story for another day.....XD)
The input voltage I can get is the full rectified type.
For signal like this, there's no way for DSP to tell whether it's the positive cycle or negative cycle. Hence increasing the difficulty in achieving the PLL. Therefore, I was thinking that I need to transform it back to the sinusoidal one. The solution I am looking for is either implemented by OPAMP or other simple circuit.

WinWin

 

[kappa_am]

elimination negative cycle give a half-wave rectified waveform. have you used a full-bridge to rectify?. if you can reach the bridge take your output of two pins of diode that is turn on in negative cycle and its cathode is connected to positive line.

to know the sign of the input voltage, you can use a voltage divider and a comparator.

Good luck

 

[FvM]

I'm not sure if your question became clearer with the last addendum.

If I got the application context right, you want to regenerate the original fundamental frequency from the (frequency doubled) full rectified waveform. We should start with a simple but necessary reservation: What ever you do, it's absolutely impossible to extract the phase of the fundamental without an N*180° uncertainty. Once you have the full rectified waveform, you can't distinguish between original positive and negative cycle.

Having said this, there are simple solutions possible. You can e.g. count halfwaves with a flip-flop and cut each second one. More generally, a Costas Loop PLL locks to the fundamental of an input signal with 180° phase uncertainty, even if it's partly covered by noise.

 

[win_win]

I'm not sure if your question became clearer with the last addendum.

If I got the application context right, you want to regenerate the original fundamental frequency from the (frequency doubled) full rectified waveform. We should start with a simple but necessary reservation: What ever you do, it's absolutely impossible to extract the phase of the fundamental without an N*180° uncertainty. Once you have the full rectified waveform, you can't distinguish between original positive and negative cycle.

You're right, it's impossible to reflect the original input status. But as long as I can provide a way to determine the sign that would be good enough.

Having said this, there are simple solutions possible. You can e.g. count halfwaves with a flip-flop and cut each second one. More generally, a Costas Loop PLL locks to the fundamental of an input signal with 180° phase uncertainty, even if it's partly covered by noise.

Could you be more specific on this, I have zero experience in using flip-flop. (I know the fundamental things, such as truth table but no practical experience)
As a hardware engineer, I don't have the authority to determine what kind of PLL to be used. Basically, all I have to do is following the request from our firmware engineer, generating the signal that is OK to tell the sign of input voltage, even with the 180 degree uncertainty.

 

[FvM]

Think! 180 degree uncertainty means that the sign of the original input voltage is lost can't be regenerated any more.

According to your present input, the problem can't be solved. Any project participant with some technical background should be able to see this. There's no purpose of discussing circuit details so far.

 

[red_alert]

Assuming that you only need to restore the sinusoidal signal (no matter what the original phase was) you could use @FvM solution.

A flip-flop is sort of an astable circuit which switches its output for every input (clock) signal. So you need a comparator with an almost zero triggering level to create an accurate clock signal for your flip-flop from that rectified signal. The output of the flip-flop will control an analogic switch (mux/demux) with two inputs: one has the original rectified signal and the other has the inverted rectified signal.

 

[win_win]

I guess I am the one who is lacking of technical background.
Hence, raising a question like this.
However, I get to learn something from it
Thanks for the time and opinion.

 

[win_win]

Thanks for the details.
I'll run the simulation and see how it goes.