Jul 16, 2007 #1 F fengluan Junior Member level 3 Joined Apr 14, 2006 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,463 For the following circuit: if Vdd=Vdc=5V ,the current is ok if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated. why for this ? and how can i eliminate osc. The start circuit i added has no effect for this . thanks .
For the following circuit: if Vdd=Vdc=5V ,the current is ok if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated. why for this ? and how can i eliminate osc. The start circuit i added has no effect for this . thanks .
Jul 16, 2007 #2 J jfyan Full Member level 2 Joined May 3, 2006 Messages 145 Helped 26 Reputation 52 Reaction score 4 Trophy points 1,298 Location shanghai,china Activity points 2,064 fengluan said: For the following circuit: if Vdd=Vdc=5V ,the current is ok if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated. why for this ? and how can i eliminate osc. The start circuit i added has no effect for this . thanks . Click to expand... hi increase the resistor value or decrease the size ratio of two nmos transistors may do work, i think. good luck jeff
fengluan said: For the following circuit: if Vdd=Vdc=5V ,the current is ok if Vdd=Vpwl(0s 0v ,1us 5V) ,then oscillate generated. why for this ? and how can i eliminate osc. The start circuit i added has no effect for this . thanks . Click to expand... hi increase the resistor value or decrease the size ratio of two nmos transistors may do work, i think. good luck jeff
Jul 16, 2007 #3 E elbadry Full Member level 6 Joined May 6, 2005 Messages 347 Helped 72 Reputation 144 Reaction score 10 Trophy points 1,298 Location Egypt Activity points 3,884 The circuit is unstable. It may need a compensation capacitor
Jul 16, 2007 #4 N nxing Advanced Member level 1 Joined May 10, 2004 Messages 421 Helped 25 Reputation 50 Reaction score 10 Trophy points 1,298 Location China Activity points 2,856 This circuit is a positive circuit if you analyze it carefully, so in order to make it not oscillating, you have to make the loop gain less than one.
This circuit is a positive circuit if you analyze it carefully, so in order to make it not oscillating, you have to make the loop gain less than one.
Jul 17, 2007 #5 F fengluan Junior Member level 3 Joined Apr 14, 2006 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,463 thanks I have simulated it ,the loop gain is -5dB, but it's still oscillate. But when decrease Width of two pmos ,then no osc. i confused for it .
thanks I have simulated it ,the loop gain is -5dB, but it's still oscillate. But when decrease Width of two pmos ,then no osc. i confused for it .
Jul 17, 2007 #6 Z zhangsai04 Junior Member level 3 Joined Mar 30, 2007 Messages 29 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,286 Activity points 1,401 Can you give the netlist?
Jul 18, 2007 #7 F fengluan Junior Member level 3 Joined Apr 14, 2006 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,463 Nmos 12u/3u m=2 m=16 Pmos 20u/3u m=2 R: 50k
Jul 19, 2007 #8 Z zhangsai04 Junior Member level 3 Joined Mar 30, 2007 Messages 29 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,286 Activity points 1,401 Try add two capacitors at the gates of pmos and nmos.
Jul 21, 2007 #9 J jankin Junior Member level 3 Joined Nov 30, 2003 Messages 27 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 96 You may try ac analysys and get the PM.
Jul 23, 2007 #10 L liuhongflyfly Newbie level 6 Joined Aug 5, 2005 Messages 14 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,353 U can ref gray's book